`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: University of Utah
// Engineer: David Hurst, Tyson Hunt, Chase Hochstrasser
// 
// Create Date:    15:38:24 09/20/2011 
// Design Name: 
// Module Name:    Counter 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description:  This is a 16 bit up-counter with sychronous active high reset.
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Counter(CLK, reset, PC_in, PC, PC_inc, PC_WE);

parameter n = 10;

input CLK, reset, PC_WE;
input [n-1:0] PC_in;

output reg [n-1:0] PC;
output [n-1:0] PC_inc;


  always @(posedge CLK)
    begin
      if (reset)
			PC = 0;
      else if (PC_WE)
			PC = PC_in;
    end
	 
assign PC_inc = PC + 1;

endmodule
